1. Field of the Invention
The present invention relates to an optical information reproduction apparatus for reproducing digital information recorded on an optical information recording medium and, more particularly, to a reproduction signal processing apparatus for reproducing digital information by sampling a reproduced binary reproduction signal in response to clock signals.
2. Related Background Art
Conventionally, as recording media on and from which information is recorded and read out using light, various forms of media such as a disk-shaped medium, a card-shaped medium, a tape-shaped medium, and the like are known. These optical information recording media include a medium which allows both recording and reproduction, a medium which allows only reproduction, and the like. In particular, since an optical card as a recording medium has many features such as easy manufacture, good portability, high accessibility, and the like, its application range is expected to widen. Various optical information recording/reproduction apparatuses for the optical card have been proposed.
In such an optical information recording/reproduction apparatus, recording/reproduction is executed while executing auto-tracking control and auto-focusing control all the time. Information is recorded on a recording medium by scanning an information track with a light beam which is modulated according to recording information and is focused to a very small spot. In this case, a series of information is recorded as an information pit array which can be optically detected. Furthermore, information is reproduced from a recording medium by scanning the information bit array on the information track with a light beam spot which has a predetermined power low enough not to cause recording, and by detecting light reflected by or transmitted through the medium.
FIG. 1 shows an example of such an information recording/reproduction system. In the system shown in FIG. 1, a light beam emitted from a semiconductor laser 101 is collimated by a collimator lens 102, and is then split into a plurality of light beams by a diffraction grating 103. The split light beams are focused on an optical card 107 via a polarization beam splitter 104, a quarterwave plate 105, and an objective lens 106. Light reflected by the optical card 107 is incident on a photodetector 109 via the objective lens 106, the quarterwave plate 105, the polarization beam splitter 104, and a toric lens 108. At this time, of the light beams split by the diffraction grating 103, a 0th-order diffracted light beam is used for performing recording, reproduction, and auto-focusing control (to be abbreviated as AF hereinafter), and .+-.1st-order diffracted light beams are used for performing auto-tracking control (to be abbreviated as AT hereinafter). The AF adopts an astigmatism method, and the AT adopts a 3-beam method.
Part (a) of FIG. 2 is a schematic plan view of the optical card. A large number of parallel information recording/reproduction tracks are formed on the optical card 107, and some (T1, T2, and T3) of these tracks are illustrated. These tracks are separated by tracking tracks tt1 to tt4. The tracking tracks tt1 to tt4 consist of a material having a different reflectance from that of the grooves or tracks T1 to T3, and are used as guides for obtaining a tracking signal. Part (a) of FIG. 2 shows a case wherein information is recorded on or reproduced from the track T3. In this case, a 0th-order diffracted light beam 110 for recording, reproduction, and AF is radiated on the track T3, and .+-.1st-order diffracted light beams 111 and 112 for AT are respectively radiated on the tracking tracks tt3 and tt4. A tracking signal to be described later is obtained from reflected light beams of the diffracted beams 111 and 112, and the AT is executed based on the tracking signal, so that the 0th-order diffracted light beam 110 correctly scans on the track T3. The diffracted light beams 110, 111, and 112 are scanned on the optical card 107 by a mechanism (not shown) in the right-and-left direction on the plane of drawing of part (a) of FIG. 2 while maintaining a predetermined positional relationship.
This scanning system includes a system for moving an optical system, and a system for moving the optical card. In either system, since the optical system and the optical card are reciprocally moved relative to each other, a non-uniform speed portion appears at the two end portions of the optical card. Part (b) of FIG. 2 shows this state. The abscissa of part (b) of FIG. 2 represents the right-and-left direction of the optical card, and the ordinate represents the scanning velocity. Normally, a constant scanning region at the central portion of the optical card 107 is used as a recording region.
FIG. 3 is a partial enlarged view of the diffracted light beams 110 to 112 shown in part (a) of FIG. 2. The 0th-order diffracted light beam 110 for recording, reproduction, and AF is located at the central position between the .+-.1st-order diffracted light beams 111 and 112 for AT, and scans the center of the track T3. Hatched portions 113a, 113b, and 113c are normally called pits which are recorded by the 0th-order diffracted light beam 110. Since the pits 113a, 113b, and 113c have a different reflectance from that of the surrounding portion, when they are scanned with a weak light spot, reflected light of the light spot is modulated by the pits 113a, 113b, and 113c, thus obtaining a reproduction signal.
FIG. 4 is a circuit diagram showing the details of the photodetector 109 shown in FIG. 1, and a signal processing circuit. Referring to FIG. 4, the photodetector 109 shown in FIG. 1 comprises a total of six photosensor portions, i.e., 4-split photosensors 114 and photosensors 115 and 116. Light spots 110a, 111a, and 112a represent reflected light beams from the optical card 107 of the diffracted light beams 110, 111, and 112 in part (a) of FIG. 2 and FIG. 3. The light spot 110a is focused on the 4-split photosensors 114, and the light spots 111a and 112a are respectively focused on the photosensors 115 and 116. The outputs from the diagonal 4-split sensors 114 are respectively added by adders 117 and 118.
The outputs from the adders 117 and 118 are added by an adder 121 to reproduce an information reproduction signal RF. More specifically, the signal RF corresponds to the sum of all the portions of the light spot 110a focused on the 4-split photosensors 114. The output from the adder 118 is subtracted from the adder 117 by a differential circuit 120 to obtain a focusing control signal Af. The signal Af corresponds to a difference between the sums of the diagonal 4-split photosensors 114. Since the astigmatism method is described in detail in other references, a detailed description thereof will be omitted. The output from the photosensor 116 is subtracted from the output from the photosensor 115 by a differential circuit 119 to obtain a tracking control signal At. Normally, control is made to set At to be zero. With this control, tracking control for scanning the light spot to follow the information track is attained.
The signal RF obtained in this manner is binarized to be recognized as digital information, and is subjected to, e.g., processing for synchronizing the signal RF with a clock signal. FIG. 5(a) is a circuit diagram showing an example of this processing circuit, and FIG. 6 is a timing chart showing signals of the respective units in FIG. 5(a) through 5(c). The output RF from the adder 121 (FIG. 4) is input to the inverting input terminal of a comparator 122 of FIG. 5(a), and is compared with a reference voltage ref1 to generate a binary reproduction signal RF2. The reproduction signal RF2 is input to a D-type flip-flop 123, and is sampled in response to a sampling clock SC which is generated by a PLL control signal generator including components 124 to 127 (to be described later), and is substantially synchronous with the signal RF2 so as to compensate for a variation in scanning velocity. The sampled reproduction signal RF is generated as signal data synchronized with the sampling clock SC. Thereafter, in general, the signal data is stored in a buffer memory under the control of the sampling clock SC. The stored signal data is demodulated by a demodulator (not shown), and is recognized as digital information (reproduction data).
On the other hand, in order to substantially synchronize the sampling clock SC with the binary reproduction signal RF2, the binary reproduction signal RF2 and the sampling clock SC are input to a phase comparator 124. FIG. 5(b) is a circuit diagram showing the detailed circuit arrangement of the phase comparator 124. The binary reproduction signal RF2 is input to the clock terminal of a D-type flip-flop 128, and outputs Q and Q' (Q' is the inverted output of Q) of the flip-flop 128 are respectively set at high and low levels. The non-inverted output Q the flip-flop 128 is input to the data terminal of a flip-flop 129, and the sampling clock SC is input to the clock terminal of the flip-flop 129. When the non-inverted output Q from the flip-flop 128 is at high level, outputs Q and Q' from the flip-flop 129 are respectively set at high and low levels.
The inverted output Q' from the flip-flop 129 is connected to the reset terminal of the flip-flop 128 to reset the flip-flop 128. Thus, the output Q from the flip-flop 128 goes to low level, and the outputs Q and Q' from the flip-flip 129 are respectively inverted to low and high levels in response to the next sampling clock SC. Therefore, the flip-flop 128 outputs a phase difference (time difference) pulse from the leading edge of the binary reproduction signal RF2 to the leading edge of the sampling clock SC, and the flip-flop 129 outputs a pulse for one period of the sampling clock SC after the binary reproduction signal RF2 rises. When the pulse for one period and the sampling clock SC are gated by an AND gate 130, a half-period pulse D is output.
This processing will be described in detail below. When the phase of the binary reproduction signal RF2 coincides with the sampling clock SC, the width of the pulse output from the flip-flop 128 corresponds to half the period of the sampling clock SC. When the phase of the sampling clock SC is delayed from that of the binary reproduction signal RF, this pulse width becomes longer than the half period; when the phase of the sampling clock SC advances from that of the binary reproduction signal RF, this pulse width becomes shorter than the half period. Therefore, an output U or U' (U' is the inverted output of U) from the flip-flop 128 can be used as a phase delay signal, i.e., a signal for increasing the frequency of the sampling clock SC, and an output D from the AND gate 130 can be used as a phase advance signal, i.e., a signal for decreasing the frequency of the sampling clock SC. In other words, the phase difference of the sampling clock SC from the binary reproduction signal RF2 is represented by the pulse width of the output U or U' from the flip-flop 128, and in this case, in order to discriminate the phase delay or advance, the output D, as the half period pulse of the sampling clock SC, from the AND gate 130 is referred to.
In order to reproduce information from a medium on which information is recorded as the length of a pit or the interval between each two adjacent pits, as described above, the period of the sampling clock SC must be equal to a minimum pit length (to be referred to as 1T hereinafter). When the pit length or interval is larger than 1T, although the sampling clock SC is input at a 1T period, the binary reproduction signal RF2 does not change, and a phase comparison with each sampling clock SC cannot be performed. Thus, in the case shown in FIG. 5(b), a phase comparison with the sampling clock SC is performed at only the leading edge of the binary reproduction signal RF2. In order to realize this operation, an SR flip-flop, which is set in response to the binary reproduction signal RF2, and is reset in response to the sampling clock SC, is required. In FIG. 5(b), this SR flip-flop operation is attained by feeding back the inverted output Q' from the D-type flip-flop 129 to the reset terminal of the flip-flop 128.
The two outputs U' and D from the phase comparator 124 are input to a charge pump/loop filter 125. FIG. 5(c) is a detailed circuit diagram of the most typical charge pump/loop filter 125. Since an operational amplifier 131 receives a reference voltage ref2, when the levels of both the two outputs U' and D 10 from the phase comparator 124 are lower than that of the reference voltage ref2, an electric charge from the output from the amplifier 131 is charged on a capacitor C1 via the capacitor C1, resistors R3 and R1, and a diode D1, and the output from the amplifier 131 becomes high. At this time, since the direction of the diode D2 is opposite to an input D, no current flows to the input D. Conversely, when the levels of both the two outputs U' and D from the phase comparator 124 are higher than that of the reference voltage ref2, a current flows from the input D to the output of the amplifier 131 via a diode D2, resistors R2 and R3, and the capacitor C1, an electric charge is discharged from the capacitor C1 in a direction opposite to the above-mentioned direction, and the output from the amplifier 131 becomes low. In this case, when the resistors R1 and R2 are set to have the same resistance, the difference between the charge and discharge amounts of the capacitor C1 is proportional to the difference between the pulse widths of the two outputs from the phase comparator 124. More specifically, when the pulse widths of the outputs U' and D from the phase comparator 124 are equal to each other, an output FC from the amplifier 131 is constant; when the pulse width of the output U' from the phase comparator 124 is larger than that of the output D, the output FC from the amplifier 131 becomes high; and when the pulse width of the output D from the phase comparator 124 is larger than that of the output U', the output FC from the amplifier 131 becomes low.
The output, obtained in this manner, from the charge pump/loop filter 125 is input to a frequency control terminal FC of the voltage-controlled oscillator (VCO) 126. As an example of the VCO 126, ICs such as SN74LS624 (trade name) available from Texas Instruments, Co., and the like are known, and these ICs output a signal of a frequency almost proportional to a frequency control input FC within a preset frequency range. The output from the VCO 126 is halved by the frequency demultiplier 127 to obtain a duty ratio of 1:1, thus generating a sampling clock SC. The generated sampling clock SC is fed back to the phase comparator 124, is used as a clock for sampling the binary reproduction signal RF2 by the flip-flop 123, and is also used as a control signal for, e.g., buffer memory control. More specifically, when the pulse width of the output U' from the phase comparator 124 is larger than that of the output D, the frequency of the sampling clock SC becomes high; when the pulse width of U' is smaller than that of D, the frequency of the sampling clock SC becomes low. When the pulse widths of the two outputs U' and D from the phase comparator 124 are equal to each other, the frequency of the sampling clock SC is left unchanged.
Note that 113d to 113f shown in FIG. 6 represent the same pits as the pits 113a to 113c shown in FIG. 3, which pits are optical marks having a lower reflectance than that of a surrounding portion. These pits often use not only an optical density difference but also diffraction of light caused by a three-dimensional pattern. The pit 113d shown in FIG. 6 is a minimum pit having a length of 1T, and the pit 113e has a length twice that of the minimum pit, i.e., 2T. The pits 113d and 113e are separated by a minimum interval of 1T, and the pits 113e and 113f are separated by an interval twice the minimum interval, i.e., 2T. FIG. 6 illustrates a case wherein the pit lengths and the pit intervals just have rated values. When the recording medium is moved relative to the light spot, and the pits are scanned by the light spot 110a in the direction of an arrow as in FIG. 3, since the pit portion has low reflectance, an RF signal shown in FIG. 6 is obtained. When the RF signal is compared with the reference voltage ref1 by the comparator 122 shown in FIG. 5(a), an inverted binary reproduction signal RF2 is obtained.
Part (a) of FIG. 6 illustrates a state wherein the binary reproduction signal RF2 is synchronized with the sampling clock SC. Each of the output signals U and D from the above-mentioned flip-flop 128 and the AND gate 130 has a pulse width half of the minimum pit length scanning time 1T, i.e., 0.5T. At this time, the leading edge of the sampling clock SC as a sampling point for sampling the binary reproduction signal RF2 is located at the center of each pit and each pit interval, and the margin for a variation in scanning velocity of the light spot is maximum. Part (b) of FIG. 6 illustrates a case wherein the sampling clock SC is delayed by 0.25T (25%) from the binary reproduction signal RF2. In this case, the above-mentioned circuit operates to increase the pulse width of the output U from the flip-flop 128 to be larger by 0.25T than the output D from the AND gate 130 so as to increase the frequency of the sampling clock SC, so that the sampling clock SC catches up with the binary reproduction signal RF2. Conversely, part (c) of FIG. 6 illustrates a case wherein the sampling clock SC advances by 0.25T (25%) from the binary reproduction signal RF2. In this case, the above-mentioned circuit operates to decrease the pulse width of the output U from the flip-flop 128 to be smaller by 0.25T than the output D from the AND gate 130 so as to decrease the frequency of the sampling clock SC, so that the sampling clock SC is adjusted backward to the binary reproduction signal RF2. In the above-mentioned cases shown in FIG. 6, since the pit lengths and intervals have rated values, and the margin at that time is 0.5T (50%), even when the clock SC and the signal RF2 are shifted by 0.25T (25%), as shown in parts (b) and (c) of FIG. 6, data 1T, 1T, 2T, and 2T can be precisely reproduced.
However, actual pit lengths and intervals do not always have rated values, and change due to various causes. For example, when a pit is formed on an optical recording medium by a light spot, the pit size varies depending on the intensity of the light spot. Even when the intensity of the light spot is set to be constant, the medium characteristics change due to a variation in environmental conditions, and the pit size also changes due to this cause. Furthermore, when a pit is pre-formatted in the manufacture of an optical recording medium, it is normally formed to have a three-dimensional pattern (protrusion/recess). In this case, the pit size changes due to manufacturing errors in mold formation or etching.
FIG. 7 shows a state wherein pits whose sizes change due to the above-mentioned causes are scanned by a light spot. Part (a) of FIG. 7 shows a case wherein the pit lengths and intervals have rated values as in FIG. 6, part (b) of FIG. 7 shows a case wherein the pit length is smaller by 0.25T (25%) than the rated value, and part (c) of FIG. 7 shows a case wherein the pit length is larger by 0.25T (25%) than the rated value. In these cases, when the pit size changes due to the above-mentioned causes, the central position or center interval of the pits is left almost unchanged. Therefore, when the pit length decreases, the interval between the end portions of two adjacent pits increases; when the pit length increases, the interval decreases. Parts (b) and (c) of FIG. 7 show this relationship.
FIGS. 8 and 9 are timing charts obtained when the pits shown in parts (b) and (c) of FIG. 7 are scanned by the conventional apparatus shown in FIG. 5. FIG. 8 corresponds to part (b) of FIG. 7, and FIG. 9 corresponds to part (c) of FIG. 7. Part (a) of FIG. 8 shows a case wherein the binary reproduction signal RF2 is synchronized with the sampling clock SC, and the pulse width of the output U from the flip-flop 128 is equal to that of the output D from the AND gate 130. At this time, as is apparent from part (a) of FIG. 8, the sampling point of the sampling clock SC is present at a position separated by 0.5T from the leading end of the pit, and the margin to the trailing end of the pit is only 0.25T. In this case, as shown in part (b) of FIG. 8, when the sampling clock SC is delayed by 0.25T (25%) from the binary reproduction signal RF2, the sampling point of the sampling clock SC is located at a position immediately before the trailing end of the pit. For this reason, when the sampling clock SC is delayed by a time longer than 0.25T (25%) even slightly, it samples not the pit but an interval portion. As a result, as indicated by DATA in part (b) of FIG. 8, original data indicated by a broken line is lost, and wrong data is sampled.
When the pit size increases, as shown in part (a) of FIG. 9, the margin of the interval portion becomes 0.25T (25%). As a result, as shown in part (b) of FIG. 9, when the sampling clock SC advances by 0.25T (25%) from the binary reproduction signal RF2, the sampling clock SC samples not the interval portion but a pit portion, thus obtaining wrong data. In this manner, in the conventional apparatus, the pit size varies by various causes, and the variation margin of 0.5T between the binary reproduction signal and the sampling clock decreases by an amount corresponding to the pit size change. Therefore, original data cannot be reproduced, or a wrong portion is sampled, and wrong data is reproduced.